Differences between revisions 261 and 369 (spanning 108 versions)

XILINX MAC 4: eth9: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN qlen 1000

link/ether 00:17:31:94:35:e5 brd ff:ff:ff:ff:ff:ff

http://re-play.cz/2011/05/cuts-2/ http://thenextweb.com/shareables/2011/06/13/watch-neil-patrick-harris-kill-it-at-the-tony-awards/ http://feeds.boston.com/click.phdo?i=000208124927907396678b525a65ed9b

For the implementation in VHDL and the subsequent synthesis, we have used the Xilinx ISE 12.3 which comes with integrated ISim VHDL simulator. The use of simulator speeds up the development but at the expense of creating testbenches which can easily become non-trivial.

The designed circuit structure is of single-clock synchronous type which is suitable for implementation in VHDL using many parallel processes all driven by common clock edge of same polarity. Some of the processes also contain asynchronous reset which is needed for the initialization and re-initialization and is synthesizable. Generics are used wherever possible to make individual parts re-usable. Unfortunately, VHDL does not allow unconstrained aggregates in record type so some of the bus widths have to be hard-coded. We have at least used constant types in such cases.

= UART and Memory Controller

The important part of the entire system is the implementaion of UART along with a memory controller. All the memories have to instantiated at the top level so the controller is able to communicate with them. This unfortunately leads to enormous number of signals which are needed for the interconnection. For simplification, a set of multiplexers and demultiplexers have been implemented. This does not lower the number of signals (in fact, it adds some) but greatly simplifies the structure of the memory controller itself. A great simplification would be achieved by usage of record type but since VHDL does not allow unconstrained types in records, we are prevented from doing this. We are still looking for a way to solve this. Let me just stress this does not change the structure itself, we're only talking about the simplicity of expression in VHDL.

= Memories

Memory entities are the core of all our table-based computational cores. It's a single-clock synchronous circuit with the ability to pump and dump data by "out-of-band" channel. This is very important since it would be non-trivial to initialize memory contents.

= Simulation

As for the simulation, the testpench consists of instantiation of all circuit parts and their interconnection using appropriate signals. A set of functions is used to read and write the input and output to a text file, respectively. We have used the std.text.io library for this data-to-text interface.

When the simulation is run, a reset is performed for a fixed amount of time. Then, the input is fed into the circuit and the output is being recorded to be later compared to the results of Matlab simulations. The clock is being generated since the beginning of the simulation and keeps running until the very end to accurately simulated the real-world conditions of the circuit.

= Synthesis

The final design has been synthesized for the Xilinx Virtex 6 FPGA and downloaded to the device itself. An important part of the synthesis process is mapping the actual hardware ports to input and output signals. This turned out to be quite tricky as the official documentation describes the pin layout only partially. We had to resolve to trial-and-error method to get the pin layout (especially for the wide buses) right.

mbaaaaak 37792717 m1m1

R791WRX9RBKH7FKK 38500601

musi mit pripravu na dalsi laborku kazdy prevodnik bude realizovan jinym typem log.obvodu, v ramci jedne realizace je nesmi michat (treba NAND a NOR dohromady proste ne)

todo amerika: esta! napsat shay napsat kate lucka plavky

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http://www.tipmoto.com/dily-moto/motory/kompletni-motor/12144-zx6-2006-motor.html
http://www.pavlicekmotordily.cz/
http://www.motorkari.cz/forum-detail/?ft=92157&fid=18
http://www.motorkari.cz/forum-detail/?ft=71577&fid=5&vrk=2932366
- Doktorand se v současnosti zabývá problematikou návrhu optimální procesorové architektury pro jednodimenzionální iterativní detekci, konkrétně detekci Turbokóku. Dále pak návrhem architektury pro iterativní sdruženou synchronizaci a detekci. V minulosti se zabýval problematikou vlivu přenosu signálu na subjektivní a objektivní kvalitu videa. Doktorand má splněnou obhajobu odborné studie i státní doktorskou zkoušku. V současné době zpracovává svou disertační práci s názvem "Návrh a optimalizace procesorové architektury pro pokročilé kódování přenosu".

nalepka na kitu:
S/N 0950-500

na ISE cdcku:
xilinx internal serial p/n 1050498-02

********************************************************
********************************************************
**     ML605 - FLASH Test                             **
********************************************************
********************************************************
-- Initialized the Flash library successfully --
-- Unlocked all the blocks successfully --
-- Erased the Flash memory contents at offset 0x1FE0000 successfully --
-- Writing: 000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F2021
22232425262728292A2B2C2D2E2F303132333435363738393A3B3C3D3E3F40414243444546474849
4A4B4C4D4E4F505152535455565758595A5B5C5D5E5F606162636465666768696A6B6C6D6E6F7071
72737475767778797A7B7C7D7E7F808182838485868788898A8B8C8D8E8F90919293949596979899
9A9B9C9D9E9FA0A1A2A3A4A5A6A7A8A9AAABACADAEAFB0B1B2B3B4B5B6B7B8B9BABBBCBDBEBFC0C1
C2C3C4C5C6C7C8C9CACBCCCDCECFD0D1D2D3D4D5D6D7D8D9DADBDCDDDEDFE0E1E2E3E4E5E6E7E8E9
EAEBECEDEEEFF0F1F2F3F4F5F6F7F8F9FAFBFCFDFEFF
-- Write operation at offset 0x1FE0000 completed successfully --
-- Read operation completed successfully --
Flash test failed (1)

********************************************************
********************************************************
**     ML605 - FLASH Test                             **
********************************************************
********************************************************
-- Fail at Initialize --
Flash test failed (1)

hgkjgjkgasdfasdfkjgj

v patek mam nocni, so ne volno...v po dlouhou, utery kratka, patek kratka a so, ne makam dlouhe

janca hospa: 8, 9, 12, 13, 17, 20, 21, 24, 26, 29, 30, 31

http://www.kawiforums.com/how-tos-faqs/106668-how-change-battery-05-06-zx-6r.html

GE 152841060 / 0600

PHOTONICS PRAGUE 2008 - The 6th International Conference on Photonics, Devices and Systems - The Iterative Detection Network Suppression of Defocusing and Thermal Noise in Black and White Pictures Shot By a Camera with CCD/CMOS Sensor - Kekrt Daniel Ing. Klíma Miloš prof.Ing. CSc. Podgorný Radek Ing.

H.264/MPEG-4 Part 10, Opticke komunikace 2007 Aspects of image quality enhancement in security technology

Klíma Miloš prof.Ing. CSc. Kekrt Daniel Ing. Podgorný Radek Ing. 42nd Annual 2008 IEEE International Conference on Security Technology

Odolnost kodeků MPEG-2 a H.264 proti chybám při přenosu Access server R.Podgorný, M.Klíma 2007

Bit Error Resilience of MPEG-2 and H.264 Video Compression Codecs, 19th International Conference RADIOELEKTRONIKA 2009, R.Podgorný, M.Klíma

Text Readability and Object Identifiability Thresholds

in H.264/AVC Video Coding Standard

Radek Podgorný, Miloš Klíma RTT 2008

ANALÝZA VYBRANÝCH KODEKŮ Z HLEDISKA POUŽITELNOSTI PRO ÚČELY BEZPEČNOSTI A

DOHLEDU

Radek Podgorný, Miloš Klíma IEEE Workshop Zvule 2007

Image Quality and QoE in Multimedia Systems Miloš KLÍMA 1 , Karel FLIEGEL 1 , Daniel KEKRT 1 , Petr DOSTÁL 1 , Radek PODGORNY 2 19th International Conference RADIOELEKTRONIKA 2009

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subject: zakazka

prosil bych nasvitit

1x pozitiv sito
1x negativ sito

z prilozeneho fajlu

http://olimex.com/dev/avr-pg1.html http://www.adafruit.com/index.php?main_page=product_info&cPath=16&products_id=47&zenid=29a419231bb9af20e090ec3bb4ffce3a http://www.ladyada.net/make/usbtinyisp/index.html

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ATmega8 1x SOKL 28 1x R 68 2x R 1.5k 1x R 10k 1x D BZX83V003.3 2x (Zener diode 3.3V) X 16Mhz 1x C 27pF 2x C 4.7uF/10V 1x C 100nF 1x Trimer 10k 1x USB1X90B PCB 1x S2G20 1x (staci 2x5 toto je 2x10 to ale neva)

Způsob úhrady: bankovní převod

Částka: 474,00 czk Platbu proveďte na účet 34175028 / 2400. SWIFT kód (pro mezinárodní platby) EBNKCZPP. IBAN CZ5824000000000034175028. Při úhradě uveďte Váš variabilní symbol: 5550035255. Variabilní symbol slouží jako identifikace Vaší objednávky.

17.4.1967 - 68703

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Fakt to funguje??????

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[03:17:00 PM] Tomas Forche: az budes v praci pak prosim precti na fixusoj /mnt/mapy/readme.txt, udelej review a pripadne podle toho uprav mapupdate skript, konfiguraci mapengine a kdo vi ceho co zere data map + pak prejmenuj adresar /data na /barrels. Zbytek si udelam sam. :-)
[03:50:00 PM] Tomas Forche: jo a uz je vyresen problem s nabihanim mapserveru... on rekurzivne proleza adresare, takze mit updates s mraky dlazdic v adresari data nebylo stastne reseni :-)))

Gianna Nannini - Meravigliosa creatura

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prdel2

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=Jasir= http://www.csclub.uwaterloo.ca/media/Riding%20The%20Multi-core%20Revolution.html

http://linuxhelp.blogspot.com/2007/02/7-habits-for-effective-text-editing-20.html http://www.andyfoulds.co.uk/amusement/bushv2.htm

<< < 2024 / 11 > >>
Mon	Tue	Wed	Thu	Fri	Sat	Sun
				1	2	3
4	5	6	7	8	9	10
11	12	13	14	15	16	17
18	19	20	21	22	23	24
25	26	27	28	29	30

http://trac.lighttpd.net/trac/ticket/894

http://trac.lighttpd.net/trac/changeset/1580

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Super vec

http://www.pendrivelinux.com/2006/03/25/new-slax-usb-install-method/

147.32.123.229

Baba Haba

k,nj

musim si to taky zkusit

Mrcarlik

''tak do toho''

solidni solidni 123 no pozrime sa na to ?i to v?bec funguje ???

asi to fakt funguje :-)))

JaR?K

Par?da!!!

d:)

no to jo ....

Huhuhu snim ci bdim ?

Demonstrace funk?nosti

No vypad? to zaj?mav? (hodn?) ...

Opravdu? nj ahojky skou?ka textu xxx

HALOOOOO.. HIHIHI..

Tak schv?ln?!

Text

Italika

Novy odstavec? Snad ano ...

Tabulka

Zahlavi tabulky
fce1	f2	f3	f4	f55
g1	g2	g3	g4

Odkazy

Odkaz na Google: http://www.google.com Odkaz na Google

Obrazek

Seznam

polozka 1
- vnorena 1.1
- * vnorena 1.2
- vnorena 1.3
polozka 2
polozka 3

boldIt`s great

***************************

//*Toto je velice uzitecna a verim ze i zabavna vec. Jsem zvedav, co budoucnost jeste prinese - do zacatku by se mohlo jednat o verejne kresleni, coz by mohlo byt opravdu vtipne :DD*//

test editace

asdfjkl? tralala, ja si tu napisu inteligentniii hlasku

*****************************

Uzasne znacky

Vhodne i pro ochocene opice jako napriklad (opice opravena):))

http://www.webbusiness.no/webprivat/usa/upfiles/bush_monkey.jpg

Jen mi hrozne vadi ti odporni graficti smajlici

aaaa Nen? to ?patn? n?pad. Vladim?r

Aaa

AAA

A

XXXXXXXXXXX

sqele

Zauj?mav?, ?eby som u n?s ?ud? prin?til robi? na webe? Aspo? nebud? ma? v?hovorku ?e som im to tam nedal... ddddddddddddddddfffffffffffffffffffffffffffffff

******* Hmm goood idea... Schvalne co to provede

to fakt nejny hl??py

Za predpokladu ze budou fungovat nejaky pristupovy prava a nebude to anarchie, by to vyuzitelny byt mohlo...

123 skuska mikrofonu ---

:-!

hmmm tak tenhle smajlik asi nefuni ... kazdopadne je to sqela vec! okamzite to zavedu v praxi! MOC DIKY ZA NAPAD! Hust?.

--- **************** celkom pekne, zacnem uvazovat na co by som to nasadil vo firme

****************

Dik, pouzivame twiki v praci jako intranet. Jindra at jeta.net

Nazev

kurziva tucne tucna kurziva

tabulka
1	2	3
a	b	c

Jan Hammer - Escape from television

Text text - You poor boy. "I dont like you!" preview

ahoj Martin, tak aj toto ide

opravuji text...

Soudruzi Revoluci. Tvoji krev my nezrad?me, lenin ten?s bude v?st, jeho odlaz nikdy nezrad?me .....

nova tabulka
1	a	2	b	3
a	a	b	b	c

193.165.104.77

=PSY2=

free running: 2047.997kHz 2048.018 - pred update 2048.017 - po update - TRIB_1 - Timing state=normal odpojeno - 2047.995 - LINE_1 zruseno LINE_1 - 2048.018 -> TRIB_1 - normal odpojeno 2048.019 - TRIB_1 - holdover

rozpad synchronizace -> LSS -> ALL1

clc;clear;close all; fd=1000; fm=8000; Wn=fd/(fm/2); N=20;

WIN_ha=hamming(N+1); B_ha=fir1(N,Wn);

WIN_b=bartlett(N+1); B_b=fir1(N,Wn,WIN_b);

WIN_bl=blackman(N+1); B_bl=fir1(N,Wn,WIN_bl);

WIN_h=hann(N+1); B_h=fir1(N,Wn,WIN_h);

figure(1) Ng=1024;

[H_ha W_ha]=freqz(B_ha,1,Ng); subplot(2,2,1); f_ha=W_ha*fm/2/pi; plot(f_ha,20*log10(abs(H_ha))); title('hamming');

[H_b W_b]=freqz(B_b,1,Ng); subplot(2,2,2); f_b=W_ha*fm/2/pi; plot(f_b,20*log10(abs(H_b))); title('bartlett');

[H_bl W_bl]=freqz(B_bl,1,Ng); subplot(2,2,3); f_bl=W_ha*fm/2/pi; plot(f_bl,20*log10(abs(H_bl))); title('blackman');

[H_h W_h]=freqz(B_h,1,Ng); subplot(2,2,4); f_h=W_h*fm/2/pi; plot(f_h,20*log10(abs(H_h))); title('hann');

return; %uloha 2 figure(2) F=[0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1]; A=[1 1 1 0 0 0 0 0 0 0 0];

Bha=fir2(N,F,A,WIN_ha); Bh=fir2(N,F,A,WIN_h);

[Hha Wha]=freqz(Bha,1,Ng); subplot(2,1,1); fha=Wha*fm/2/pi; plot(fha,20*log10(abs(Hha))); title('hamming');

[Hh Wh]=freqz(Bh,1,Ng); subplot(2,1,2); fh=Wh*fm/2/pi; plot(fh,20*log10(abs(Hh))); title('hann');

%uloha 3 impulsni odezva figure(3) impz(Bha,1);

%uloha 3 f char figure(4) freqz(Bha,1,Ng,fm/2);

%uloha 3 f char figure(5) zplane(Bha,1)

a) poplach v: RDI v MS, HP, LP protoze komunikace analyzator-AM1 byla jednosmerna

SOH f6 f6 f6 28 28 28 01 aa aa 46*ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 68 93 93 00 ff ff 00 00 00 e3*08*41*00 ff ff 06 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0b ff ff ff ff 00 ff ff ff

LO-POH V5: 65* J2: 00 N2: 00 K4: 00

b) zadne alarmy

c) pointer u tu-12 received se snizuje ptr au-4 = 0

0: 2e-4 1: 3e-4 5: 9e-4 10: 1.55e-3 20: 2.95e-3 50: 7.15e-3 100: 1.42e-2 200: 2.82e-2

pro taktovani z prijimaneho signalu = 0

d) count/secs HP REI: 9767/20 = 3.249e-6 LP REI: 1257/20 = 2.806e-5 SLIP: 20/20 = 1

ES: 0 SES: 0 US: 20 100% DM: 0 EFS: 0 BE: 0 AE: 0

1 Lucie Dvorakov- 2 Veronika Klusov- 3 Veronika Krskov- 4 Alena Dvorakov- 5 Marketa Vavrov-? 6 Jana Pflegerov- 7 Alena Bockschneiderov- 8 Daniela Beckov- 9 Zuz_x_ana Mi_x_sar_x_kov- 10 Zdenka Kral_x_ikova 11 Bara Musilov- 12 Blanka Cizkov- 13 Lucie Sim_x_unk_x_ova 14 Li_x_buska Step_x_anko_x_va 15 Eva Sa_x_sova? 16 Dan_x_iela Cer_x_na 17 Alej_x_andra Urdi_x_ain 18 Pe_x_tra F_x_enclo_x_va 19 Al_x_ena Prch_x_alova (roc_x_k cafe) 20 Ven_x_dula Mus_x_ilova 21 El_x_isab_x_eth Wa_x_lch 22 Ve_x_ra Dyt_x_rtova

clear;clc; fv=8000

t=0:1/fv:0.6-1/fv; y1=0.4*sin(2*pi*300*t); y2=0.6*sin(2*pi*2500*t); y=y1+y2; n=2; fv1=n*fv xinterp=zeros(1,n*length(y)); xinterp(([1:length(y)]-1)*n+1)=y;

figure(1); subplot(2,2,1); %title('Neinterpolovany') ffty1=abs(fft(y))/length(y); stem(0:fv/length(ffty1):fv-fv/length(ffty1),ffty1);

subplot(2,2,2); %title('Interpolovany') ffty2=abs(fft(xinterp))/length(xinterp); stem(0:fv1/length(ffty2):fv1-fv1/length(ffty2),ffty2);

N=60; B=fir1(N,fv/2/(fv1/2)); subplot(2,2,3); xinterp_filtered=filter(B,1,xinterp); ffty3=abs(fft(xinterp_filtered))/length(xinterp_filtered); stem(0:fv1/length(ffty3):fv1-fv1/length(ffty3),ffty3);

fv2=fv/n

B=fir1(N,fv2/2/(fv/2)); y=filter(B,1,y);

subplot(2,2,4); indxs=1:n:length(y); y_decim=y(indxs); ffty4=abs(fft(y_decim))/length(y_decim); stem(0:fv2/length(ffty4):fv2-fv2/length(ffty4),ffty4);

brigde - 4ms 1 hop

route - 4ms 172.20.20.20 172.20.20.1 172.33.1.2 172.32.32.10

1.2km GS DSP version :1 xDSL GS Version :R.1.5 xDSL side :COE. Startup Progress :(0x0)Startup not in progress. Operation state :Data. Operation rate :2320 Kbps Framer Sync. state :Framer in SYNC Last fail state :No failure. SNR margin value :3 DB. Loop attenuation :11 DB. Receice Gain :10 DB. Transmit Power :14 dBm. xDSL state :DSL_ACTIVE

2.4km GS DSP version :1 xDSL GS Version :R.1.5 xDSL side :COE. Startup Progress :(0x0)Startup not in progress. Operation state :Data. Operation rate : 656 Kbps Framer Sync. state :Framer in SYNC Last fail state :No failure. SNR margin value :1 DB. Loop attenuation :18 DB. Receice Gain :7 DB. Transmit Power :13 dBm. xDSL state :DSL_ACTIVE

-77dBm/Hz

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http://www.openstreetmap.org/edit.html?lat=55.929313&lon=-4.336938&zoom=14

http://dusky.sk/halbot/?id=2157

http://www.acc.umu.se/~bosse/

http://www.zvon.cz/translations/cathedral-bazaar/Output/contents_cs.html

http://www.pixelbeat.org/cmdline.html

http//www.blastwavecomic.com

Bara, Ilona, Urna, Tomik, Vlasac, Svata

snova přednášek Digitální sítě, předmět fakultní nabídky FEL, šk. r. 2006/07 Osnova přednášek 1. 05. 10. Druhy signálů. Digitalizace signálu. Základní pojmy. Fyzický a virtuální kanál 2. 12. 10. Multiplexní principy. Hierarchie PDH 3. 19. 10. Hierarchie SDH, její podstata, funkce a formáty 4. 26. 10. Referenční model OSI RM. Vrstvy, protokoly, formáty 5. 02. 11. Adresové multiplexy. Vývoj X 25, FR, IP, ATM, DQDB 6. 09. 11. Digitální přenosové trakty. Opakovače. Linkové kódy. Optické linkové trakty 7. 16. 11. Spojovací zařízení a jejich členění. Účastnické bloky. Rozhraní ústředny 8. 23. 11. Digitální síť integrovaných služeb (ISDN). Druhy spojení a služby ISDN 9. 30. 11. Širokopásmová síť integrovaných služeb (ATM). Referenční model. Třídy služeb 10. 07. 12. Principy a realizace spojovacích polí v úzkopásmových a v širokopásmových sítích 11. 14. 12. Síťové prvky. Parametry přenosu a spojení. Spojovací prvky 12. 21. 12. Signalizace - členění. Účastnická signalizace. Síťová signalizace 13. 04. 01. Státní regulace telekomunikací. Síťové plány 14. 11. 01. Mezinárodní standardy a doporučení

:8888 http tunnel na lokalni :22 (ssh) :10022 redirect na lokalni :22 (ssh)

(Praha) http_proxy=http://proxy:3128 ./tilesGen.pl xy 2212 1388

-  ⇤ ← Revision 261 as of 2007-06-10 12:28:33 → 
  Size: 10998
  Editor: RadekPodgorny
  Comment:
+   ← Revision 369 as of 2011-12-07 13:54:56 → ⇥
  Size: 24363
  Editor: RadekPodgorny
  Comment:
-Deletions are marked like this.
+Additions are marked like this.
 Line 2:
-== hgkjgjkgkjgj ==
+XILINX MAC
4: eth9: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN qlen 1000
    link/ether 00:17:31:94:35:e5 brd ff:ff:ff:ff:ff:ff

http://re-play.cz/2011/05/cuts-2/
http://thenextweb.com/shareables/2011/06/13/watch-neil-patrick-harris-kill-it-at-the-tony-awards/
http://feeds.boston.com/click.phdo?i=000208124927907396678b525a65ed9b

For the implementation in VHDL and the subsequent synthesis, we have used the
Xilinx ISE 12.3 which comes with integrated ISim VHDL simulator. The use of
simulator speeds up the development but at the expense of creating testbenches
which can easily become non-trivial.

The designed circuit structure is of single-clock synchronous type which is
suitable for implementation in VHDL using many parallel processes all driven
by common clock edge of same polarity. Some of the processes also contain
asynchronous reset which is needed for the initialization and
re-initialization and is synthesizable. Generics are used wherever possible to
make individual parts re-usable. Unfortunately, VHDL does not allow
unconstrained aggregates in record type so some of the bus widths have to be
hard-coded. We have at least used constant types in such cases.

= UART and Memory Controller

The important part of the entire system is the implementaion of UART along
with a memory controller. All the memories have to instantiated at the top
level so the controller is able to communicate with them. This unfortunately
leads to enormous number of signals which are needed for the interconnection.
For simplification, a set of multiplexers and demultiplexers have been
implemented. This does not lower the number of signals (in fact, it adds some)
but greatly simplifies the structure of the memory controller itself. A great
simplification would be achieved by usage of record type but since VHDL does
not allow unconstrained types in records, we are prevented from doing this. We
are still looking for a way to solve this. Let me just stress this does not
change the structure itself, we're only talking about the simplicity of
expression in VHDL.

= Memories

Memory entities are the core of all our table-based computational cores. It's
a single-clock synchronous circuit with the ability to pump and dump data by
"out-of-band" channel. This is very important since it would be non-trivial to
initialize memory contents.

= Simulation

As for the simulation, the testpench consists of instantiation of all circuit
parts and their interconnection using appropriate signals. A set of functions
is used to read and write the input and output to a text file, respectively.
We have used the std.text.io library for this data-to-text interface.

When the simulation is run, a reset is performed for a fixed amount of time.
Then, the input is fed into the circuit and the output is being recorded to be
later compared to the results of Matlab simulations. The clock is being
generated since the beginning of the simulation and keeps running  until the
very end to accurately simulated the real-world conditions of the circuit.

= Synthesis

The final design has been synthesized for the Xilinx Virtex 6 FPGA and
downloaded to the device itself. An important part of the synthesis process is
mapping the actual hardware ports to input and output signals. This turned out
to be quite tricky as the official documentation describes the pin layout only
partially. We had to resolve to trial-and-error method to get the pin layout
(especially for the wide buses) right.



mbaaaaak 37792717 m1m1

R791WRX9RBKH7FKK
38500601

musi mit pripravu na dalsi laborku
kazdy prevodnik bude realizovan jinym typem log.obvodu, v ramci jedne realizace je nesmi michat (treba NAND a NOR dohromady proste ne)

todo amerika:
esta!
napsat shay
napsat kate
lucka plavky



 * http://www.motorkari.cz/forum-detail/?ft=87884&fid=18
 * http://www.brusirnapavlicek.cz/index.php?hlavnitext=reference
 * http://www.motorkari.cz/motobazar/nahradni-dily/motory/motory-zx6r-zx10r-1000rr-211876.html
 * http://www.motorkari.cz/motobazar/nahradni-dily/motory/dily-z-motoru-kawasaki-zx-6-r-209590.html
 * http://www.motorkari.cz/motobazar/nahradni-dily/motory/prodam-motor-zx-6r-05-a-07-195950.html
 * http://www.tipmoto.com/dily-moto/motory/kompletni-motor/?znacka=kawasaki
 * http://www.tipmoto.com/dily-moto/motory/nekompletni-motor/24040-motorove-dily-zx-636r.html
 * http://www.tipmoto.com/dily-moto/motory/kompletni-motor/12144-zx6-2006-motor.html
 * http://www.pavlicekmotordily.cz/
 * http://www.motorkari.cz/forum-detail/?ft=92157&fid=18
 * http://www.motorkari.cz/forum-detail/?ft=71577&fid=5&vrk=2932366


  Doktorand se v současnosti zabývá problematikou návrhu optimální procesorové architektury pro jednodimenzionální iterativní detekci, konkrétně detekci Turbokóku. Dále pak návrhem architektury pro iterativní sdruženou synchronizaci a detekci. V minulosti se zabýval problematikou vlivu přenosu signálu na subjektivní a objektivní kvalitu videa.
  Doktorand má splněnou obhajobu odborné studie i státní doktorskou zkoušku. V současné době zpracovává svou disertační práci s názvem "Návrh a optimalizace procesorové architektury pro pokročilé kódování přenosu".


{{{
nalepka na kitu:
S/N 0950-500

na ISE cdcku:
xilinx internal serial p/n 1050498-02
}}}

{{{
********************************************************
********************************************************
**     ML605 - FLASH Test                             **
********************************************************
********************************************************
-- Initialized the Flash library successfully --
-- Unlocked all the blocks successfully --
-- Erased the Flash memory contents at offset 0x1FE0000 successfully --
-- Writing: 000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F2021
22232425262728292A2B2C2D2E2F303132333435363738393A3B3C3D3E3F40414243444546474849
4A4B4C4D4E4F505152535455565758595A5B5C5D5E5F606162636465666768696A6B6C6D6E6F7071
72737475767778797A7B7C7D7E7F808182838485868788898A8B8C8D8E8F90919293949596979899
9A9B9C9D9E9FA0A1A2A3A4A5A6A7A8A9AAABACADAEAFB0B1B2B3B4B5B6B7B8B9BABBBCBDBEBFC0C1
C2C3C4C5C6C7C8C9CACBCCCDCECFD0D1D2D3D4D5D6D7D8D9DADBDCDDDEDFE0E1E2E3E4E5E6E7E8E9
EAEBECEDEEEFF0F1F2F3F4F5F6F7F8F9FAFBFCFDFEFF
-- Write operation at offset 0x1FE0000 completed successfully --
-- Read operation completed successfully --
Flash test failed (1)
}}}

{{{
********************************************************
********************************************************
**     ML605 - FLASH Test                             **
********************************************************
********************************************************
-- Fail at Initialize --
Flash test failed (1)
}}}

== hgkjgjkgasdfasdfkjgj ==
v patek mam nocni, so ne volno...v po dlouhou, utery kratka, patek kratka a so, ne makam dlouhe :-(

janca hospa: 8, 9, 12, 13, 17, 20, 21, 24, 26, 29, 30, 31

http://www.kawiforums.com/how-tos-faqs/106668-how-change-battery-05-06-zx-6r.html

{{http://www.boingboing.net/2010/01/11/Star%20Wars%20Girls_-40-1-thumb-550x367.jpg}}

{{http://i15.tinypic.com/4r94841.jpg}}

GE 152841060 / 0600

PHOTONICS PRAGUE 2008 - The 6th International Conference on Photonics, Devices and Systems -  	The Iterative Detection Network Suppression of Defocusing and Thermal Noise in Black and White Pictures Shot By a Camera with CCD/CMOS Sensor - Kekrt Daniel Ing. Klíma Miloš prof.Ing. CSc. Podgorný Radek Ing.

  H.264/MPEG-4 Part 10, Opticke komunikace 2007

  Aspects of image quality enhancement in security technology
Klíma Miloš prof.Ing. CSc.  	Kekrt Daniel Ing.  	Podgorný Radek Ing. 42nd Annual 2008 IEEE International Conference on Security Technology

Odolnost kodeků MPEG-2 a H.264 proti chybám při přenosu Access server   R.Podgorný, M.Klíma 2007

Bit Error Resilience of MPEG-2 and H.264 Video Compression Codecs, 19th International Conference RADIOELEKTRONIKA 2009, R.Podgorný, M.Klíma

Text Readability and Object Identifiability Thresholds
       in H.264/AVC Video Coding Standard
Radek Podgorný, Miloš Klíma
RTT 2008

ANALÝZA VYBRANÝCH KODEKŮ Z HLEDISKA
POUŽITELNOSTI PRO ÚČELY BEZPEČNOSTI A
              DOHLEDU
Radek Podgorný, Miloš Klíma
IEEE Workshop Zvule 2007


Image Quality and QoE in Multimedia Systems
Miloš KLÍMA 1 , Karel FLIEGEL 1 , Daniel KEKRT 1 , Petr DOSTÁL 1 , Radek PODGORNY 2
19th International Conference RADIOELEKTRONIKA 2009



192292756 / 0600

917377
ciman8


{{{
DISPALARM:OBJECT=LNLCKOUT,ALSTAT=NP,ALPRIO=CRITICAL,RSUINF=YES;
}}}

== nosice kol ==
 * http://www.neumax.cz/menu/pujcovna/
 * http://www.stresninosice.cz/cz/menu/sluzby/pujcovna/
 * http://www.nosicekol.cz/pujcovna.php
 * http://www.boxy.cz/pujcovna.html

adsfasdf
asdfasdf
adfasdfaf
'''adfasd'''sdfasdfadfadf df adf adf as'''adf sd fsdf adf adf adsf''adf sd df'''''
-Line 4:
+Line 206:
+||<tablewidth="200px"> || ||
|| || ||
|| || ||


http://gme.cz/cz/index.php?page=product&detail=511-773 2x

{{{
subject: zakazka

prosil bych nasvitit

1x pozitiv sito
1x negativ sito

z prilozeneho fajlu
}}}


http://olimex.com/dev/avr-pg1.html
http://www.adafruit.com/index.php?main_page=product_info&cPath=16&products_id=47&zenid=29a419231bb9af20e090ec3bb4ffce3a
http://www.ladyada.net/make/usbtinyisp/index.html

http://tme.cz/katalog/index.phtml?id_g=16&id_p=31&id2=20&id_drzewo=554&from=index
http://www.iinchip.com/pro_iin_NM7010B.htm

ATmega8           1x
SOKL 28           1x
R 68              2x
R 1.5k            1x
R 10k             1x
D BZX83V003.3     2x    (Zener diode 3.3V)
X 16Mhz           1x
C 27pF            2x
C 4.7uF/10V       1x
C 100nF           1x
Trimer 10k        1x
USB1X90B PCB      1x
S2G20             1x      (staci 2x5 toto je 2x10 to ale neva)


Způsob úhrady: bankovní převod

Částka: 474,00 czk
Platbu proveďte na účet 34175028 / 2400.
SWIFT kód (pro mezinárodní platby) EBNKCZPP.
IBAN CZ5824000000000034175028.
Při úhradě uveďte Váš variabilní symbol: 5550035255.
Variabilní symbol slouží jako identifikace Vaší objednávky.




17.4.1967 - 68703



30.04.2007 - 7000
31.05.2007 - 6000
02.07.2007 - 6000
31.07.2007 - 10000
01.10.2007 - 6000
02.11.2007 - 3000
05.12.2007 - 3000
11.12.2007 - 1785
31.12.2007 - 8000
31.01.2008 - 3000
03.03.2008 - 3000



http://www.naep.cz/index.php?a=view-project-folder&project_folder_id=123&view_type_code=document&general_file_id=2566&


http://www.youtube.com/watch?v=BwzVvVK4G6Y
-Line 5:
+Line 283:
+ * http://portal.isiknowledge.com/portal.cgi
-Line 6:
+Line 286:
+ * http://www.faqs.org/faqs/compression-faq/part2/index.html
 * http://www.faqs.org/faqs/compression-faq/part2/section-8.html
 * http://videocodecs.blogspot.com/

C82GA-C28UA-GEQ2A-3Q6WI-SEGY0

[[http://rozvrh.fsv.cvut.cz/stranky3/FSvTTable.asp?identifier=A6-7(A6-1)&PrintStyle=individual&WeekStartNo=2&WeekEndNo=15&weeks=2-15&days=1-5&PeriodStartNo=1&PeriodEndNo=14&periods=1-14&idtype=id&objectclass=student+sets&heigth=100&width=100|http://rozvrh.fsv.cvut.cz/stranky3/FSvTTable.asp?identifier=A6-7%28A6-1%29&PrintStyle=individual&WeekStartNo=2&WeekEndNo=15&weeks=2-15&days=1-5&PeriodStartNo=1&PeriodEndNo=14&periods=1-14&idtype=id&objectclass=student+sets&heigth=100&width=100]]

http://www.ddworld.cz/windows/icq-cesky-masochismus-v-im-instant-messagingu.html

http://www.gpsweb.cz/JTSK-WGS.htm

http://tinderbox.dev.gentoo.org/default-linux/amd64/

http://www.linuxdriver.co.il/kernel_map

{{http://im.super.cz/disc/50/25/705-1-orig.jpg}}

http://www.kernel.org/pub/linux/kernel/people/tglx/hrtimers/

http://sandbox.cz/aekdxxxx

{{attachment:kun.gif}}

{{http://macphisto.nepracuje.cz/pub/topolepsie.gif}}

http://pbfcomics.com/?cid=PBF093AD-Cave_Explorer.jpg#160

http://www.super.cz/vtipky/8562-turecky-rambo.html

http://books.google.com/books?hl=en&lr=&id=DwcDm6xgItUC&oi=fnd&pg=PR13&dq=vector+quantization+compression&ots=touPnVsRhK&sig=VFrnS9dGh6nLqFKolO6Sza2LtN8#PPA631,M1

{{http://www.ce4you.cz/files/forums/cz/0000167478/2463_startrek-bluescreen-1.gif}}

http://www.novinky.cz/zena/zdrav/na-nemoci-srdce-a-cev-zemre-mesicne-5000-lidi_121649_3n2kh.html

http://www.vcodex.com/h264.html
-Line 13:
+Line 329:
+{{http://halbot.haluze.sk/images/2005-05/1034_how_make_crossovercable.jpg}}
-Line 18:
+Line 336:
-attachment:linux-detergent.jpg
+{{attachment:linux-detergent.jpg}}
-Line 24:
+Line 342:
-http://www.bangedup.com/archives/rotten.jpg
+{{http://www.bangedup.com/archives/rotten.jpg}}
-Line 32:
+Line 350:
-:) :( =Jasir= http://www.csclub.uwaterloo.ca/media/Riding%20The%20Multi-core%20Revolution.html
+:) :( =Jasir= [[http://www.csclub.uwaterloo.ca/media/Riding%20The%20Multi-core%20Revolution.html|http://www.csclub.uwaterloo.ca/media/Riding%20The%20Multi-core%20Revolution.html]]
-Line 36:
+Line 354:
-[[MonthCalendar()]]
+<<MonthCalendar>>

{{http://halbot.haluze.sk/images/2004-03/7_CALENDARIO_KAMASUTRA_2004.jpg}}

{{http://im.super.cz/disc/41/92/922-1-orig.jpg}}
-Line 49:
+Line 371:
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-http://www.srandy.sk/obrazky/59.jpg
+{{http://www.srandy.sk/obrazky/59.jpg}}
-Line 91:
+Line 414:
-Line 92:
+Line 417:
- . Odkaz na Google: http://www.google.com Odkaz na [http://www.google.com Google]
+ . Odkaz na Google: http://www.google.com Odkaz na [[http://www.google.com|Google]]
-Line 94:
+Line 420:
-http://www.ms.mff.cuni.cz/~dolej1am/img/smoke4.jpg
+{{http://www.ms.mff.cuni.cz/~dolej1am/img/smoke4.jpg}}
-Line 103:
+Line 429:
-Line 118:
+Line 445:
-[http://www.webbusiness.no/webprivat/usa/upfiles/bush_monkey.jpg]
+http://www.webbusiness.no/webprivat/usa/upfiles/bush_monkey.jpg
-Line 134:
+Line 461:
-Line 138:
+Line 466:
-Line 152:
+Line 481:
-Dik, pouzivame [http://www.twiki.org twiki] v praci jako intranet. Jindra at jeta.net
+Dik, pouzivame [[http://www.twiki.org|twiki]] v praci jako intranet. Jindra at jeta.net
-Line 161:
+Line 490:
+{{http://starosta.com/ebay/betty2820_A.jpg}}
-Line 162:
+Line 495:
-Text text - You poor boy. "I dont like you!" [http://podgorny.cz/moin/SandBox#preview preview]
+Text text - You poor boy. "I dont like you!" [[http://podgorny.cz/moin/SandBox#preview|preview]]
-Line 174:
+Line 507:
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+Line 513:
-Line 186:
+Line 522:
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+Line 557:
-Line 236:
+Line 574:
+Lucie Dvorakov-
2 Veronika Klusov-
3 Veronika Krskov-
4 Alena Dvorakov-
5 Marketa Vavrov-?
6 Jana Pflegerov-
7 Alena Bockschneiderov-
8 Daniela Beckov-
9 Zuz_x_ana Mi_x_sar_x_kov-
10 Zdenka Kral_x_ikova
11 Bara Musilov-
12 Blanka Cizkov-
13 Lucie Sim_x_unk_x_ova
14 Li_x_buska Step_x_anko_x_va
15 Eva Sa_x_sova?
16 Dan_x_iela Cer_x_na
17 Alej_x_andra Urdi_x_ain
18 Pe_x_tra F_x_enclo_x_va
19 Al_x_ena Prch_x_alova (roc_x_k cafe)
20 Ven_x_dula Mus_x_ilova
21 El_x_isab_x_eth Wa_x_lch
22 Ve_x_ra Dyt_x_rtova
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+Line 599:
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+{{attachment:kozy.jpg}}
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